1. Field of the Invention
The present invention relates to an interrupt control system and a storage control system using that interrupt control system. More specifically, the present invention relates to an interrupt control system using Message Signal Interrupts (hereinafter abbreviated to “MSIs”), and a storage control system using that interrupt control system.
2. Description of Related Art
Conventional storage control systems include: a host control LSI that controls communication with information processing apparatuses; a (storage) disk control LSI that controls communication with storage devices; cache memory; a data transfer control LSI; and an MP control unit. The data transfer control LSI serves as a bridge between the host control LSI and the MP control unit, or as a bridge between the disk control LSI and the MP control unit, for control information (e.g. data input/output requests), and also conducts control for data transfer between the host control LSI and the cache memory, or data transfer between the disk control LSI and the cache memory. The MP control unit controls the host control LSI, disk control LSI and data transfer LSI, in response to control information (e.g. data input/output requests) from host apparatuses.
The host control LSI and the disk control LSI each have conventionally been configured to be connected to the data transfer control LSI via PCI buses, and to send interrupts to the MP control unit via interrupt signal lines according to events that occur internally.
As art related to the above type of interrupt control, for example, Japanese Patent Laid-open Publication No. 07-084970 discloses an interrupt control method that aims at improving performance in data processing by preventing data processing in a CPU from being interrupted based on an interrupt sent to that CPU when that CPU is not the CPU for executing processing for the device where the interrupt originated. This interrupt control method is characterized in that, in a data processing method for a system having a plurality of CPUs and a plurality of devices wherein each CPU executes data processing for predetermined device(s), an interrupt controller for recognizing, when an interrupt signal is output from one device, the interrupt source device, and an interrupt table for setting the association between the devices and the CPUs in the interrupt controller are provided.
Also, an interrupt control system for a computer system disclosed in Japanese Patent Laid-open Publication No. 09-097177 aims at minimizing the number of signal lines used for transferring a plurality of interrupt signals in a personal computer such as a laptop computer or a notebook computer where an extension unit can be used, thereby increasing the number of signals available in the extension unit and simplifying the wiring configuration of the signal lines in the system. This system is an interrupt control system for a computer system that inputs a plurality of interrupt signals and has an interrupt controller for recognizing the type of use set in advance for each interrupt signal, and the system is characterized in having: interrupt encoder means for converting a plurality of interrupt signals to serial data, the interrupt signals being sent from a source device that makes an interrupt request to a processor; serial transfer means for transferring the serial data; and interrupt decoder means for converting the serial data transferred from the serial transfer means to the original interrupt signals, and giving those interrupt signals to the interrupt controller.
Also, an invention disclosed in Japanese Patent Laid-open Publication No. 2001-331329 aims at providing an interrupt control method and interrupt control apparatus that can dynamically respond to various situations and constantly achieve optimum system performance, and it is characterized in: monitoring the system status; setting a dynamically variable number of device interrupts collected when generating a processor interrupt, based on the monitoring result; generating a processor interrupt by collecting the set number of device interrupts; and outputting the processor interrupt to a processor.